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3 v/5 v, 12/14-bit nano dac tm d/a with 10 ppm/c max on-chip reference in sot-23 prelim inary technical data ad5620/ad5640 rev. pr a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features ad56 20: low p o wer single 12- bit nano da c ad56 40: low p o wer single 16- bit nano da c 12-bit accu racy gu aranteed on-chip 1.25 v / 2.5 v, 1 0 ppm/c refer e nce tiny 8- lead sot-23/msop package power-down to 200 n a @ 5 v, 50 na @ 3 v 3 v/5 v single p o wer supply guarantee d 1 6 - bit monotonic by design power-on reset to zero/midscale 3 power-down functions serial interf ace with schmitt-t r iggered input s rail-to-rail ope r ation sync interrupt facility applic ati o ns process control data acq u isitio n systems portable batter y -powered inst ruments digital gain and offset adjustment programmable voltage an d current sources programmable attenuators func ti on a l bl ock di a g r a m ad5620/ad5640 v refout gnd ref(+) v dd resistor network power-down control logic dac register power-on reset 1.25/2.5v ref output buffer dac input control logic v out v fb sync sclk din 04781-0-001 fi g u r e 1 . general description the ad5620 /40 p a r t s a r e a m e m b er o f t h e na no da c f a m i l y o f de vices. th e y a r e lo w p o w e r , sing le , 12-/14 - b i t b u f f er e d v o l t a g e- o u t d a cs, g u a r a n t e e d m o n o t o nic b y desig n . the ad5620 /40x -1 op e r a t e f r om a 3 v s i ng l e s u ppl y f e a t u r i n g a n i n te r n a l re f e re nc e o f 1.25 v and an in t e r n al gain o f 2. the ad56 20/40x -2/3 o p er a t e f r o m a 5 v sin g l e s u p p l y f e a t ur in g a n in t e r n al r e f e r e n c e o f 2.5 v a nd a n in t e r n al ga in o f 2. e a c h ref e r e n c e has a 1 0 p p m /c max t e m p era t ur e co ef f i cien t. th e r e fer e n c e as s o ci a t e d wi t h e a ch p a r t i s av a i l a b l e at t h e r e f o u t p i n . t h e p a r t i n c o r p or a t e s a p o we r - on re s e t c i rc u i t , w h i c h e n su re s tha t t h e d a c ou t p u t p o w e rs u p t o 0 v (ad56 20/40x-1/2) o r t o mids cale (ad5 620/40x-3) a nd r e ma in s t h er e u n til a valid wr i t e t a k e s place. the p a r t con t a i n s a p o w e r - do w n fe a t ure t h a t r e d u ce s th e c u r r en t co ns um p t io n o f t h e de vice t o 200 na a t 5 v and p r o v ide s s o f t war e s e le c t ab le o u t p u t lo ads whil e in p o w e r - do wn mo d e . the ad5620 /40 us es a v e rs a t ile 3-wir e s e r i al in ter f ace tha t o p e r at e s at c l o c k r a t e s u p t o 3 0 m h z a n d i s c o mp at i b l e w i t h s t anda r d s p i?, qs p i ?, mi cr o w ire?, an d ds p in ter f ace st anda r d s. i t s on-ch i p p r e c isio n o u t p u t am plif ier a l lo ws ra i l -to- ra il o u t p u t swing t o be achieved. the lo w p o w e r co n s um p t io n o f t h is p a r t in n o r m a l o p era t io n m a k e s i t i d e a ll y s u i t e d t o po r t a b l e ba t t e r y- o p e r a t ed eq ui p m en t . the p o wer co n s um p t ion is 0.7 mw a t 5 v , r e d u cin g t o 1 w in p o w e r - do wn mo de. the ad5620 /40 is desig n e d wi t h new t e c h n o log y a n d is t h e n e xt g e n e ra t i o n t o th e ad53xx f a m i l y . related de vices part no. description ad5660 3 v/5 v 16-bit d a c in sot-23, internal reference ad5662 2 . 7 v to 5 . 5 v 1 6 - b i t d a c i n so t-2 3 , e x ter n a l re f e r e n c e product highlights 1. 16-b i t d a c; 12-b i t acc u rac y gua r a n t e e d . 2. on-c hi p 1.25 v/2.5 v , 10 p p m/c max r e f e r e n c e . 3. a v ai lab l e i n 8 - l e ad s o t - 23 and 8-l e a d msop p a ck a g es. 4. p o we r - on re s e t to 0 v or m i d s c a l e . 5. p o wer - do w n c a p a b i l i t y . w h e n p o wer e d do w n , t h e d a c typ i c a l l y co n s u m es 50 na a t 3 v a nd 200 na a t 5 v . 6. 10 s s e t t lin g tim e .
ad5620/ad5640 preliminary technical data rev. pra | page 2 of 20 table of contents ad5620/40x-2/3Cspecifications ..................................................... 3 ad5620/40x-1Cspecifications ........................................................ 5 timing characteristics ..................................................................... 7 pin configuration and function descriptions ............................. 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 ter mi nolo g y .................................................................................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 14 serial interface ............................................................................ 14 microprocessor interfacing ....................................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 10/04revision 0: pra
preliminary technical data ad5620/ad5640 rev. pra | page 3 of 20 ad5620/40x-2/3Cspecifications v dd = +4.5 v to +5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. parameter a grade b grade c grade unit b version 1 conditions/comments static performance 2 ad5620 resolution 12 12 12 bits min relative accuracy 6 1 1 lsb max see figure 4. differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design. see figure 5. ad5640 resolution 14 14 14 bits min relative accuracy 8 4 4 lsb max see figure 4. differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design. see figure 5. zero code error +5 +5 +5 mv typ all 0s loaded to dac register. +20 +20 +20 mv max offset error 10 10 10 mv typ full-scale error ?0.15 ?0.15 ?0.15 % of fs r typ all 1s loaded to dac register. ?1.25 ?1.25 ?1.25 % of fsr max gain error 1.25 1.25 1.25 % of fsr max zero code error drift 3 2 2 2 v/c typ gain temperature coefficient 2.5 2.5 2.5 ppm typ of fsr/c dc power supply rejection ratio ?100 ? 100 ?100 db typ dac code = midscale; v dd = 5 v 10% output characteristics 3 output voltage range 0 0 v min v dd v dd v dd v max output voltage settling time 8 8 8 s typ to 0.003% fsr 0x0200 to 0xfd00 10 10 10 s max r l = 2 k?; 0 pf < c l < 200 pf 12 12 12 s typ r l = 2 k?; c l = 500 pf slew rate 1 1 1 v/s typ capacitive load stability 2 2 2 nf typ r l = 10 10 10 nf typ r l = 2 k? output noise spectral density 80 80 80 nv/hz typ dac code = midscale, 10khz output noise (0.1 hz to 10 hz) 10 10 10 vp-p typ dac code = midscale thd, total harmonic distor tion ?80 ?80 ?80 db typ v ref = 2 v 300 mv p-p, f = 5 khz output drift ppm/c typ digital-to-analog glitch impulse 5 5 5 nv-s typ 1 lsb change around major carry. digital feedthrough 0.1 0.1 0.1 nv-s typ dc output impedance 0.5 0.5 0.5 ? typ short circuit current 30 30 30 ma typ v dd = 5 v power-up time 4 4 4 s typ coming out of power-down mode. v dd = 5 v reference output output voltage ad5620/40x-2/3 2.495 2.495 2.495 v min 2.505 2.505 2.505 v max reference tc 25 25 10 ppm/c max logic inputs 3 input current 1 1 1 a max 1 temperature ranges are as follows: b version: -40c to +105c, typical at 25c. 2 linearity calculated usin g a reduced code ra nge of 512 to 65024. output unloaded. 3 guaranteed by design and characterization, not production tested.
ad5620/ad5640 preliminary technical data rev. pra | page 4 of 20 parameter a grade b grade c grade unit b version 1 conditions/comments v inl , input low voltage 0.8 0.8 0.8 v max v dd = 5 v v inh , input high voltage 2 2 2 v min v dd = 5 v pin capacitance 3 3 3 pf max power requirements v dd 4.5 4.5 4.5 v min all digital inputs at 0 v or v dd i dd (normal mode) 5.5 5.5 5.5 v max da c active and excluding load current v dd = 4.5 v to 5.5 v 0.5 0.5 0.5 ma typ v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1 1 1 ma max v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.2 0.2 0.2 a typ v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1 1 1 a max v ih = v dd and v il = gnd power efficiency i out /i dd 89 89 89 % i load = 2 ma, v dd = 5 v
preliminary technical data ad5620/ad5640 rev. pra | page 5 of 20 ad5620/40x-1Cspecifications v dd = 2.7 v to 3.6 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter a grade b grade c grade unit b version 4 conditions/comments static performance 5 ad5620 resolution 12 12 12 bits min relative accuracy 6 1 1 lsb max see figure 4. differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design. see figure 5. ad5640 resolution 14 14 14 bits min relative accuracy 8 4 4 lsb max see figure 4. differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design. see figure 5. zero code error +5 +5 +5 mv typ all 0s loaded to dac register +20 +20 +20 mv max offset error 10 10 10 mv typ full-scale error ?0.15 ?0.15 ?0.15 % of fs r typ all 1s loaded to dac register. ?1.25 ?1.25 ?1.25 % of fsr max gain error 1.25 1.25 1.25 % of fsr max zero code error drift 6 20 20 20 v/c typ gain temperature coefficient 5 5 5 ppm typ of fsr/c dc power supply rejection ratio ?100 ? 100 ?100 db typ dac code = midscale; v dd = 3 v 10% output characteristics 3 output voltage range 0 0 v min v dd v dd v dd v max output voltage settling time 8 8 8 s typ to 0.003% fsr 0200 h to fd00 h 10 10 10 s max r l = 2 k?; 0 pf < c l < 200 pf. 12 12 12 s typ r l = 2 k?; c l = 500 pf slew rate 1 1 1 v/s typ capacitive load stability 2 2 2 nf typ r l = 10 10 10 nf typ r l = 2 k? output noise spectral density 80 80 80 nv/hz typ dac code = midscale, 10 khz output noise (0.1 hz to 10 hz) 10 10 10 vp-p typ dac code = midscale thd, total harmonic distor tion ?80 ?80 ?80 db typ v ref = 2 v 300 mv p-p, f = 5 khz output drift tbd ppm/c typ digital-to-analog glitch impulse 5 5 5 nv-s typ 1 lsb change around major carry. digital feedthrough 0.1 0.1 0.1 nv-s typ dc output impedance 0.5 0.5 0.5 ? typ short circuit current 30 30 30 ma typ v dd = 3 v power-up time 10 10 10 p s typ coming out of power-down mode. v dd = 3 v reference output output voltage ad5620/40x-1 1.248 1.248 1.248 v min 1.252 1.252 1.252 v max reference tc 25 25 10 ppm/c max 4 temperature ranges are as follows: b version: -40c to +105c, typical at 25c. 5 linearity calculated usin g a reduced code ra nge of 485 to 64714. output unloaded. 6 guaranteed by design and characterization, not production tested.
ad5620/ad5640 preliminary technical data rev. pra | page 6 of 20 parameter a grade b grade c grade unit b version 4 conditions/comments logic inputs 3 input current 1 1 1 a max v inl , input low voltage 0.8 0.8 0.8 v max v dd = 3 v v inh , input high voltage 2 2 2 v min v dd = 3 v pin capacitance 3 3 3 pf max power requirements v dd 2.7 2.7 2.7 v min all digital inputs at 0 v or v dd i dd (normal mode) 3.6 3.6 3.6 v max da c active and excluding load current v dd = 2.7 v to 3.6 v 0.5 0.5 0.5 ma typ v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1 1 1 ma max v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 2.7 v to 3.6 v 0.2 0.2 0.2 a typ v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1 1 1 a max v ih = v dd and v il = gnd power efficiency i out /i dd i load = 2 ma, v dd = 3 v
prelim inary technical data ad5620/ad5640 r e v. pr a | pa g e 7 of 20 timing characteristics al l in p u t s i g n als a r e s p ecif ie d wi th tr = tf = 1 n s /v (10 % t o 90 % o f v dd ) a n d t i m e d f r o m a vol t a g e le vel o f (v il + v ih )/2. se e f i g u r e 2 . v dd = 2.7 v t o 5.5 v ; al l sp ecif ic a t io n s t min to t max , u n l e ss ot he r w i s e note d. table 3. limit at t min , t ma x parameter v dd = 2. 7 v to 3. 6 v v dd = 3.6 v to 5 . 5 v unit conditions/comments t 1 7 50 33 ns min sclk cycle time t 2 13 13 ns min sclk high time t 3 13 13 ns min sclk low time t 4 0 0 ns min sync to sclk falling edge setup time t 5 5 5 ns min data setup time t 6 4.5 4.5 ns min data hold time t 7 0 0 ns min sclk falling edge to sync rising edge t 8 50 33 ns min minimum sync high time t 9 13 13 ns min sync rising edge to sclk fall ignore t 10 0 0 ns min sclk falling edge to sync fall ignore 7 ma xi m u m s c lk fre q uen c y i s 30 mh z a t v dd = 3.6 v to 5.5 v and 20 mhz at v dd = 2.7 v to 3.6 v. din sync sclk db15 db0 t 9 t 10 t 4 t 3 t 2 t 7 t 6 t 5 t 1 t 8 04781-0-002 f i gure 2. s e r i a l w r ite o p er ati o n
ad5620/ad5640 prelim inary technical data r e v. pr a | pa g e 8 of 20 pin conf igura t ion and fu nction descriptions v dd 1 v refout 2 v fb 3 v out 4 gnd 8 din 7 sclk 6 sync 5 ad5620/ ad5640 top view (not to scale) 04781-0-003 f i g u re 3. 8-l e ad s 0 t - 23/m s op p i n con f ig ur at i o n ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 v dd power supply in put. t h ese parts can be oper a te d from 2.5 v to 5.5 v, and v dd sho u ld be de-coupled to gnd. 2 v ref o u t reference voltage output. 3 v fb feedback con n e ction for the output amplifier. 4 v ou t analog output voltage from dac. the output amplifier h a s rai l -to-rail operation. 5 sync level triggered control input (active low). this is the frame sync hronizat i o n sign al for the input data. when sync goes low , it ena b les the in put shift register and d a ta is transferred in on the falli ng ed ges of the follo wing clock s . the dac is updated follo wing the 16th clock cycle, unl e s s sync is taken high before this edge ; in which case, the risi ng edge of sync acts as an interrupt, an d the write sequence is ignor e d by the dac. 6 sclk serial clock input. data is cl ocked into the input shift regi ster on the falling edge of the serial cl ock input. data can be transferred at rates up to 30 mhz. 7 din serial data inpu t. this device has a 16-bit shift register. data is clocked into the regi ster on the falling edge of the serial c l ock i n put. 8 gnd ground reference point for all circuitry on the part.
prelim inary technical data ad5620/ad5640 r e v. pr a | pa g e 9 of 20 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 5. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v ou t to gnd ?0.3 v to v dd + 0.3 v operating tem p erature range industrial (b versio n) ?40c to +105c storage temperature range ?65c to +150c j u nction temperature (t j max) 150c sot-23 package power dissi pati on ( t j max ? t a )/ ja ja thermal impedance 240c/w lead temperature, soldering vapor phase (60 s) 215c infrared (15 s) 220c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5620/ad5640 preliminary technical data rev. pra | page 10 of 20 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 4. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 5. zero-code error it is a measure of the output error when zero code (0x000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5620/ad5640 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. a plot of the zero-code error vs. temperature can be seen in figure 8. full - scale error it is a measure of the output error when full-scale code (0xfff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of the full-scale error vs. temperature can be seen in figure 8. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale range. tot a l un a dju s te d e r ror ( t u e ) tue is a measure of the output error taking all the various errors into account. a typical tue vs. code plot can be seen in figure 6. zero - code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital - to - analog glitch impulse it is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-secs and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7ff to 0x800). see figure 21. digital feedthrough it is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv-secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
prelim inary technical data ad5620/ad5640 r e v. pr a | pa g e 11 o f 20 typical perf orm ance cha r acte ristics f i g u re 4. a d 56 20 t y pic a l inl p l ot f i g u re 5. a d 56 20 t y pic a l d n l p l ot f i gure 6. a d 56 20 t y pic a l t o ta l u n adju s t ed e rror ( t u e ) p l o t f i gure 7. inl e rror and d n l e rror v s . t e mper atur e f i gure 8. zero -s c a l e e rror and f u ll- s c a l e e r r o r v s . t e mpe r a t ur e fi g u r e 9 . i dd his t og r a m wit h v dd = 3 v and v dd = 5 v
ad5620/ad5640 prelim inary technical data r e v. pr a | pa g e 12 o f 20 f i gure 10. s o urc e and sink curr ent capabilit y with v dd = 3 v f i gure 11. s o urc e and sink curr ent capabilit y with v dd = 5 v f i gure 12. sup p l y current v s . code f i gure 13. sup p l y current v s . t e mper at ur e f i gure 14. sup p l y current v s . sup p ly v o ltag e f i gure 15. p o wer - d o wn cur r ent vs. su p p ly v o ltage
prelim inary technical data ad5620/ad5640 r e v. pr a | pa g e 13 o f 20 f i gure 16. sup p l y current v s . l o gic i n p u t v o ltag e f i g u re 17. f u ll- s c al e s e t t ling ti me f i g u re 18. h a lf -s c a l e s e t t ling ti me f i gure 1 9 . p o wer - o n reset t o 0 v f i gur e 2 0 . exi t i n g p o w e r - d o wn (0 x800 l o a d e d ) f i g u re 21. d i g i t a l- t o -a na log g l i t ch i m puls e
ad5620/ad5640 prelim inary technical data r e v. pr a | pa g e 14 o f 20 theor y of opera tion d/a se ction the ad5620 /ad5640 d a c is f a b r ic a t e d o n a cm os p r o c es s. the a r c h i t ec t u re co n s is ts o f a s t r i n g d a c f o l l o w ed b y a n o u t p u t b u f f er a m p l if ier . the p a r t s inc l u d e a n in t e r n al 1. 25 v/2.5 v , 10 p p m /c r e f e r e n c e wi t h a n in ter n al ga in o f 2. f i gur e 22 sh o w s a b l o c k d i a g ra m o f t h e d a c a r chi t e c t u r e . v dd v out gnd resistor string ref (+) ref (?) [ output amplifier dac regis te r 04781-0-022 v fb f i gu r e 2 2 . d a c a r ch i t ectu r e since t h e in pu t co di n g t o t h e d a c is st ra ig h t b i na r y , t h e i d e a l out p ut vol t age i s g i ve n b y u u 65536 2 d vref v out w h er e: d e q uals t h e de cimal e q u i vale n t o f th e b i na r y co de tha t is lo aded t o t h e d a c r e g i s t er ; 0 ? 4095 f o r ad5620 (12 b i t) a nd 0 ? 16383 f o r ad5640 (14 b i t). n eq ual s t h e d a c r e so l u ti o n . r r r r r to output amplifier 04781-0-023 f i gur e 2 3 . resi st or str i ng resistor string the r e sis t o r s t r i n g s e c t ion is sho w n in f i gur e 2 3 . i t is sim p l y a s t r i n g o f r e sis t o r s, eac h o f val u e r . th e co de lo aded t o t h e d a c r e g i s t er deter m i n es a t w h ich n o de o n t h e s t r i n g t h e v o l t a g e is t a p p e d o f f t o b e fe d in t o t h e ou t p u t a m pl if ier . t h e v o l t a g e is t a pp e d of f b y cl o s i n g one of t h e s w itc h e s c o n n e c t i ng t h e st r i ng t o t h e am plif ier . b e ca us e i t is a st r i n g o f r e sist o r s, i t is g u ar an te e d monoton i c . out p ut amplifier t h e o u t p u t b u f f er a m p l if ier is ca p a b l e o f g e n e ra tin g ra il-t o-ra il vo lt age s on it s o u tput , w h i c h g i ve s an output r a nge of 0 v to v dd . i t is ca p a b l e o f dr i v in g a lo ad o f 2 k? in p a ral l e l wi t h 1000 pf t o gnd . th e s o ur ce and sin k c a p a b i l i ties o f th e ou t p u t a m p l if ier can be s e en in f i gur e 10 a nd f i gur e 1 1 . the s l ew ra t e is 1 v/s wi t h a half-s c a le s e t t lin g tim e o f 8 s wi th t h e o u t p u t unlo aded . serial interf a c e the ad5620 /ad5640 has a 3-wir e s e r i al in t e r f ace ( sy n c , sclk, and din ) , w h ich is co m p a t i b l e w i t h s p i , qs pi, an d mi cro w ire i n t e r f ac e st anda rds as w e l l as m o st ds p s . s e e f i gur e 2 f o r a timin g dia g ram o f a typ i cal wr i t e seq u en ce . the wr i t e s e q u e n ce b e g i n s b y b r in g i n g t h e sy n c lin e lo w . d a t a f r o m t h e d i n li n e is clo c k e d i n to t h e 24- b i t sh if t r e g i st er o n t h e fa l l in g e d ge o f s c lk. the s e r i a l clo c k f r e q uen c y ca n b e as hi g h as 30 mh z, ma kin g t h e ad562 0/ad5640 com p a t i b l e wi t h hig h s p eed d s p s . o n th e 24th falli n g c l oc k ed g e , t h e la s t da ta b i t i s c l oc k e d in a n d t h e p r ogra mm ed fun c ti o n i s e x ecu t ed , i . e . , a c h a n g e in d a c r e g i s t er co n t en ts a nd/o r a c h ang e in t h e mo de o f o p era t io n. a t this s t a g e , t h e sy n c line can b e k e pt lo w o r ca n be b r o u g h t hig h . i n e i t h er cas e , i t m u s t be b r o u g h t hig h fo r a minim u m o f 33 n s bef o r e t h e next wr i t e s e q u en ce s o tha t a fallin g e d g e o f sy n c ca n i n i t i a t e t h e n e xt wr i t e s e q u en c e . si n c e th e sy n c b u f f er dra w s m o r e c u r r en t w h en v in = 2.4 v tha n i t do es w h e n v in = 0.8 v , sy n c sh o u ld be idle d lo w be tw e e n wr i t e s e q u ences fo r e v en lo w e r p o w e r o p era t ion o f t h e p a r t . a s is m e n t ion e d p r e v i o u sly , h o we ver , i t m u st b e b r o u g h t h i g h a g a i n j u s t b e fo r e t h e next wr i t e s e q u e n ce. input shift r e gister the in p u t s h if t r e g i s t er is 16 b i ts wide (s ee f i gu r e 24 a n d f i gur e 25). th e f i rst tw o b i ts a r e co n t r o l b i ts, w h ich co n t r o l t h e mo d e of op e r a t i o n t h a t t h e p a r t i s i n ( n or m a l m o d e or an y o n e o f th e th r e e po w e r - d o wn m o de s). f o r a m o r e co m p le t e des c r i p t io n o f t h e v a r i o u s m o des, s e e t h e p o w e r - d o wn m o des s e c t io n. th e n e xt 14/12 b i ts a r e t h e da t a b i ts. th es e a r e t r a n sfer r e d t o t h e d a c r e g i st er o n t h e 16t h fal l i n g e d ge o f sclk.
prelim inary technical data ad5620/ad5640 r e v. pr a | pa g e 15 o f 20 data bits db15 (msb) dbo (lsb) pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 04781-0-024 f i gur e 2 4 . ad56 20 input re gi st er c o nte n ts data bits db15 (msb) dbo (lsb) pd1 pd0 d11 d10 d13 d12 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 04781-0-025 f i gur e 2 5 . ad56 40 input re gi st er c o nte n ts 04781-0-026 din db 15 db 15 d b 0 db0 invalid write sequence: sync high before 16 th falling edge valid write sequence, output updates on the 16 th falling edge sync sclk f i g u re 26. sy nc interr up t f a ci lit y sync interrupt i n a n o rm al w r i t e seq u en ce , t h e sy n c line is k e p t l o w f o r a t le ast 16 fa l l i n g e d ges o f sclk, and t h e d a c is up d a te d o n t h e 16th fal l i n g e d g e . h o wev e r , if sy n c is b r o u g h t hig h bef o r e the 16th fal l i n g e d g e , this ac ts as a n in t e r r u p t t o t h e wr i t e s e q u ence . the s h if t r e g i s t e r is r e s e t a nd t h e wr i t e s e q u e n c e is s e en as in valid . n e i t her a n u p da t e o f t h e d a c r e g i s t er co n t en ts o r a c h a n g e in t h e op era t in g m o de o c c u rs (s ee f i gu r e 26). power-on res e t the ad5620 /ad5640 fa mil y c o n t a i n s a p o w e r - o n -r es et cir c ui t, w h ich co n t r o ls t h e o u t p ut v o l t a g e d u r i ng p o w e r - u p . th e ad5620/ad56 40x-1/ad5620 /ad5640x-2 d a c o u t p u t p o w e rs u p t o 0 v , an d t h e ad5620/ad5640x-3 d a c ou t p u t p o w e rs u p t o mids cale . the o u t p u t r e ma ins th er e u n til a v a lid wr i t e s e q u e n ce is m a de t o t h e d a c. this is us ef u l i n a p plic a t io n s w h er e i t is im p o r t a n t t o k n o w t h e st a t e o f t h e ou t p ut o f t h e d a c wh ile i t i s in t h e p r oce s s o f po w e ri n g u p . power-down modes the ad5620 /ad5640 fa mil y c o n t a i n s f o ur s e p a ra t e m o des o f o p era t ion. th es e m o des a r e s o f t wa r e -p r o g r a mma b l e b y s e t t i n g tw o b i ts, d b 15 a nd d b 14, in t h e co n t r o l r e g i s t er . t a b l e 6 sh o w s h o w t h e s t a t e o f t h e b i ts co r r es p o n d s t o t h e mo de o f o p era t ion of t h e d e v i c e . table 6. modes of operation for the ad562 0 / ad5640 o p erating mo de db 15 db 14 normal ope rati on 0 0 pow e r-down modes 1 k? to gnd 0 1 100 k? to gnd 1 0 three-state 1 1 w h en b o t h b i ts a r e s e t t o 0, t h e p a r t w o rks n o r m al l y wi t h i t s n o r m al p o w e r c o n s um p t io n o f 250 a a t 5 v . h o w e v e r , f o r the thr e e p o w e r - do wn m o des, t h e su p p l y c u r r en t fa l l s t o 200 na a t 5 v a nd t o 0 na a t 3 v . n o t o n l y do es t h e s u p p l y c u r r en t fal l , b u t t h e o u tput st age i s i n te r n a l ly s w itc h e d f r om t h e output of t h e am pl i f i e r to a re s i stor ne t w or k of k n ow n v a lu e s . t h i s h a s t h e ad van t a g e t h a t t h e o u t p ut i m p e dan c e o f t h e p a r t is kno w n w h il e t h e p a r t is i n p o w e r - do w n m o de . th er e a r e t h re e dif f er en t opt i ons . t h e output i s c o n n e c te d i n te r n a l ly to g n d t h rou g h a 1 k? r e sis t o r , a 100 k? r e sis t o r , o r lef t o p en-circ u i t e d (thr ee- s t a t e). th e o u t p u t s t a g e is i l l u s t ra t e d in f i gur e 27. r esi st o r ne t w o r k v out v fb r esi st o r s t ri ng dac 04781-0-027 p o we r - d o wn ci rcui t r y a m p l ifie r f i gure 27. o u tput s t age d u r i ng p o wer-d o wn
ad5620/ad5640 prelim inary technical data r e v. pr a | pa g e 16 o f 20 the b i as g e n e ra t o r , t h e ou t p u t am plif ier , t h e r e sis t o r s t r i ng, an d th e o t h e r a s socia t e d lin e a r ci r c ui tr y a r e s h u t do wn w h en po w e r - d o w n m o d e i s acti v a t e d . h o w e v e r , th e co n t en t s o f th e d a c r e g i s t er a r e una f fe c t e d w h e n i n p o w e r - do wn. th e t i m e t o exi t p o w e r - do wn is typ i c a l l y 2.5 s f o r v dd = 5 v a nd 5 s f o r v dd = 3 v . s e e f i gur e 20. micr oprocessor interf a c ing ad5620/ad5640 to adsp-2 101/ adsp-2103 interface f i gur e 28 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5620/ad5640 a nd t h e ads p -2 101/ads p -2103 . the ads p -210 1/ads p -2103 s h o u l d b e s e t up t o o p era t e in t h e s p or t t r a n s m i t a l t e r n a t e f r a m in g mo de . the ads p -210 1/ads p -2103 s p o r t is pro g r a m m e d t h rou g h t h e sp o r t c o n t ro l re g i ste r an d s h ou l d b e co nf igur e d as fol l o w s: in t e r n a l clo c k o p era t io n, ac t i v e lo w f r a m in g, and 16 -b i t w o r d len g t h . t r a n smission i s ini t i a t e d b y wr i t in g a w o r d to th e tx r e g i s t er a f t e r s p o r t is ena b led. ad5620/ ad5640* *additional pins omitted for clarity tfs dt sclk sync din sclk 04781-0-028 adsp-2101/ adsp-2103* f i gur e 2 8 . ad56 20 /ad5 64 0 t o adsp -21 0 1 / adsp -2 103 inte r f a c e ad5620/ad5640 to 68hc1 1/68l11 interface f i gur e 29 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5620/ad5640 a nd t h e 68h c1 1/68l11 micr o c o n tr ol ler . sck o f th e 68h c11/68l11 dr i v es t h e scl k o f the ad562 0/ad5640, whil e t h e mos i ou t p u t dr i v es t h e s e r i al da t a li n e o f t h e d a c. th e sy n c sig n al is der i v e d f r o m a p o r t lin e (pc7). th e s e t-u p co ndi t i on s fo r co r r e c t o p era t ion o f t h is i n t e r f ace a r e as fol l o w s: th e 68 h c 11/68 l11 s h o u l d be c o nf igur ed s o tha t i t s cpo l b i t is 0 a n d i t s c p h a b i t i s 1. w h en da ta tra n sm i t s t o th e d a c , th e sy n c line is tak e n lo w (pc7). w h en th e 68 h c 11/68 l11 is co nf igur ed as abo v e, da t a a p p e a r in g o n t h e mos i o u t p u t is v a l i d on t h e f a l l i ng e d g e of s c k . s e r i a l d a t a f r om t h e 68h c11/68l11 tra n smi t s in 8 - b i t b y t e s wi t h o n ly eig h t f a l l in g c l o c k e d g e s o c c u r r i n g in t h e tra n smi t c y c l e . d a t a tra n smi t s ms b f i rs t. i n o r der t o lo ad da ta t o t h e ad5620/ad56 40, pc7 is lef t l o w af te r t h e f i r s t e i g h t b i t s are t r ans f e r re d, and a s e c o nd s e r i a l wr i t e o p er a t io n is p e r f o r m e d to t h e d a c and p c 7 is t a k e n hig h a t t h e e nd o f t h i s p r o c e d ur e. ad5620/ ad5640* *additional pins omitted for clarity pc7 sck mosi sync sclk din 04781-0-029 68hc11/68l11* f i gur e 2 9 . ad56 20 /ad5 64 0 t o 68 h c 11/ 68 l11 inte r f a c e ad5620/ad5640 to 80c51/ 80l51 interface f i gur e 30 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5620/ad5640 a nd t h e 80c51 /80l51 micr o c on tr ol ler . th e s e t u p f o r th e in t e r f ace is as f o l l o w s: t x d o f t h e 80c51 /80l5 1 dr i v es scl k o f th e ad5620 /ad5640, whil e r x d dr i v es t h e s e r i al da ta l i n e o f t h e p a r t . the sy n c sig n a l is a g a i n de r i ve d f r o m a b i t - pro g r a m m a bl e pi n on t h e p o r t . i n t h i s c a s e , p o r t l i ne p 3 . 3 i s us ed . w h en da t a tra n smi t s t o t h e ad5620/ad5640, p3.3 is tak e n lo w . th e 80c51/80l51 tr a n smi t s da t a o n l y in 8-b i t b y t e s; th us o n l y eig h t f a l l in g c l o c k edges o c c u r in t h e t r a n smi t c y c l e . t o lo ad da ta t o th e d a c, p3 .3 is lef t lo w a f t e r t h e f i rs t e i g h t b i ts a r e t r a n smi t te d , a nd a s e co nd w r i t e c y cle is ini t i a te d to t r a n smi t t h e s e c o n d b y t e o f d a ta . p 3 . 3 i s ta k e n h i gh f o ll o w i n g th e co m p letio n o f t h is c y c l e . th e 8 0 c51/80l51 o u t p u t s t h e s e r i a l da ta in a f o r m a t tha t has t h e ls b f i rs t. th e ad5620/ad5640 r e q u ir es i t s da ta wi th ms b f irst. the 80c51/80l 51 tra n smi t r o u t ine sh o u ld t a k e t h is in t o ac c o un t. 80c51/80l51* ad5620/ ad5640* *additional pins omitted for clarity p3.3 txd rxd sync sclk din 04781-0-030 f i gur e 3 0 . ad56 20 /ad5 64 0 t o 80 c51/8 0 l 5 1 int e r f a c e ad5620/ad5640 to microwire interface f i gur e 31 sh o w s a n in t e r f ac e b e tw een t h e ad53 20 a nd an y mi cro w ire- co m p a t i b le de vi ce. s e r i a l da t a is shif te d o u t on t h e fal l i n g e d g e o f t h e s e r i al clo c k an d is clo c k e d in t o t h e ad5320 o n t h e r i sin g edg e o f t h e s k . microwire* ad5620/ ad5640* *additional pins omitted for clarity cs sk so sync sclk din 04781-0-031 f i gur e 3 1 . ad56 20 /ad5 64 0 t o micr ow ire int e r f a c e
prelim inary technical data ad5620/ad5640 r e v. pr a | pa g e 17 o f 20 outline dimensions 1 3 5 6 2 8 4 7 2. 90 bs c 1. 60 bs c 1.95 bsc 0. 6 5 bs c 0. 3 8 0. 2 2 0. 15 m a x 1. 30 1. 15 0. 90 seating plane 1. 45 m a x 0. 22 0. 08 0. 6 0 0. 4 5 0. 3 0 8 4 0 2. 8 0 bs c pin 1 indicato r compliant to jedec standards mo-178ba f i g u re 32. 8-l e ad s m a l l o u t l i n e t r ans i s t or p a ck ag e [so t - 23] (rj-8) di me nsio n sho w n in mi ll im et e r s 0.80 0.60 0.40 8 0 4 85 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa f i g u re 33. 8-l e ad m i ni s m al l o u t l ine p a ck ag e [m sop ] (rm-8) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model grade power - on reset to internal reference package description package options b r a n d i n g d e s c r i p t i o n ad5620arj-1 a zero 1.25 v sot-23 rj-8 d2k 2 lsb inl, 25 p p m/c ref ad5620arj-2 a zero 2.5 v sot-23 rj-8 d2l 2 lsb inl, 25 p p m/c ref ad5620brj-1 b zero 1.25 v sot-23 rj-8 d2h 1 lsb inl, 25 p p m/c ref ad5620brj-2 b zero 2.5 v sot-23 rj-8 d2j 1 lsb inl, 25 p p m/c ref ad5620crj-1 c zero 1.25 v sot-23 rj-8 d2m 1 lsb inl, 25 p p m/c ref ad5620crj-2 c zero 2.5 v sot-23 rj-8 d2n 1 lsb inl, 10 p p m/c ref ad5620crj-3 c midscale 2.5 v sot-23 rj -8 d2p 1 lsb inl, 10 p p m/c ref ad5620crm-1 c zero 1.25 v msop rm-8 d2m 1 lsb inl, 10 p p m/c ref ad5620crm-2 c zero 2.5 v msop rm-8 d2n 1 lsb inl, 10 p p m/c ref ad5620crm-3 c midscale 2.5 v msop rm-8 d2p 1 lsb inl, 10 p p m/c ref ad5640arj-1 a zero 1.25 v sot-23 rj-8 d2s 8 lsb inl, 25 p p m/c ref ad5640arj-2 a zero 2.5 v sot-23 rj-8 d2t 8 lsb inl, 25 p p m/c ref ad5640brj-1 b zero 1.25 v sot-23 rj-8 d2q 4 lsb inl, 25 p p m/c ref ad5640brj-2 b zero 2.5 v sot-23 rj-8 d2r 4 lsb inl, 25 p p m/c ref ad5640crj-1 c zero 1.25 v sot-23 rj-8 d2u 4 lsb inl, 25 p p m/c ref ad5640crj-2 c zero 2.5 v sot-23 rj-8 d2v 4 lsb inl, 10 p p m/c ref ad5640crj-3 c midscale 2.5 v sot-23 rj -8 d2w 4 lsb inl, 10 p p m/c ref ad5640crm-1 c zero 1.25 v msop rm-8 d2u 4 lsb inl, 10 p p m/c ref ad5640crm-2 c zero 2.5 v msop rm-8 d2v 4 lsb inl, 10 p p m/c ref ad5640crm-3 c midscale 2.5 v msop rm-8 d2w 4 lsb inl, 10 p p m/c ref
ad5620/ad5640 preliminary technical data rev. pra | page 18 of 20 notes
preliminary technical data ad5620/ad5640 rev. pra | page 19 of 20 notes
ad5620/ad5640 prelim inary technical data r e v. pr a | pa g e 20 o f 20 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . pr04781C0C10/0 4 (pr a )

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